Job Details

divh2VP of Silicon Engineering/h2pSF Bay Area/ph3Summary/h3pWere a well-funded, stealth startup building a new computing platform based on a high-performance edge SoC on an advanced process node. Our V1 strategy is lean and aggressive: we license best-in-class IP from Arm and others, and partner with a tier-1 ASIC design service for backend execution and physical design./ppWe need a VP of Silicon who wont let external partners grade their own homework. Your immediate job is to build the team to own the development of a world-class SoC architecture, negotiate and integrate cutting-edge IP, and aggressively manage our ASIC partner to ensure they deliver top-tier PPA. Long-term, your mandate is to lay the groundwork for taking on more silicon design responsibilities in future iterations, gradually transitioning us from an IP integrator to a full-stack custom silicon company./ph3Responsibilities/h3ullistrongBuild the Core Team./strong For V1, you will hire a lean, highly capable internal team of performance architects, low-power circuit experts, system-level DV engineers, and bring-up specialists to validate the architecture and keep the ASIC partner on the path of excellence. You will also lay the structural groundwork for bringing more front-end design in-house in future iterations./lilistrongDrive System Architecture./strong You will own the overarching architectural strategy. Youll make the hard executive calls to balance strict power constraints with massive performance and memory bandwidth targets./lilistrongChallenge the Defaults./strong Relying on an ASIC partners defaults leads to missed opportunities. You and your team will actively push back on implementation choices, interrogate timing closure strategies, and force custom mitigation efforts rather than accepting sub-optimal work./lilistrongObsess Over Power and Performance./strong We have unyielding targets for performance and for both active efficiency and retention power. You will build a culture that models performance and runs traces early to ensure all bottlenecks are identified before RTL freeze and direct the evaluation of advanced low-power circuit techniques and adaptive voltage scaling (AVS) strategies./lilistrongOwn the Lifecycle./strong Your responsibility spans from early IP evaluation through product integration. You will drive post-silicon validation, silicon characterization, and hardware debug strategy, ensuring the chip meets all PPA targets and integrates seamlessly with the broader hardware and system software teams./li/ulh3Requirements/h3ullistrongDeep Silicon Track Record./strong 15+ years of engineering experience with multiple tapeouts on advanced process nodes. You deeply understand the physical and electrical characteristics of bleeding-edge manufacturing./lilistrongASIC/Turnkey Experience./strong Proven track record of successfully driving complex SoCs through an ASIC design service. You know exactly where external partners cut corners and how to catch them./lilistrongMastery of the Arm Ecosystem./strong Deep, systemic expertise in Arm architectures, interconnect fabrics, and performance analysis tooling./lilistrongExecutive Leadership and Scaling./strong 5+ years directing silicon engineering organizations. You know how to start lean, recruit elite talent, and scale an organization as internal responsibilities expand./lilistrongVendor Management./strong You are comfortable holding partners accountable. You know how to extract the best possible support, IP deliverables, and custom implementations from large external organizations./li/ulh3Salary Benefits/h3ulli$375,000/year base salary + top-of-market equity/liliPlatinum medical/dental/vision (100% employee premium coverage, 70% dependents)/lili401(k) + FSA/liliTake-what-you-need unmetered PTO/li/ul/div