Job Details

Hello Team,

Please share the profiles for below requirement and kindly let me know if you any questions.

Senior ASIC DFT CDC Constraints Eng Milpitas, CA - Remote

Candidate can be based anywhere in US but willing to work in PST time zone.

Job Description:

Senior Clock Domain Crossing (CDC) Contractor to support our engineering team. This is a critical, focused on maintaining design integrity during a transition period. The ideal candidate will serve as a subject matter expert in CDC analysis and ASIC Design-for-Test (DFT) constraints.

leading the CDC/RDC (Clock Domain Crossing / Reset Domain Crossing)

methodology in silicon one chips

Design & implement robust and reusable RTL with CDC/RDC considerations

Spec comprehensive CDC/RDC check flows and work with CAD team to implement

Review and approve CDC/RDC constraints and waivers

Perform static glitch analysis

Improve design with prevention of static glitch harzad.

Minimum Qualifications

Bachelor's or Master's degree on Electrical Engineering with at least 10 years of experience on

ASIC chip design

RTL development skills and experiences

Solid understanding on CDC/RDC concepts and relevant design implementation

Experience on maintaining CDC/RDC flow and signing-off constraints and waivers

Solid understanding on static glitch harzads and experience on the relevant analysis on synthesis optimized gate netlists

Experiences on Static Timing Analysis

Experiences on VCS simulation SVA (SystemVerilog Assertions).